AMD is bringing back its cache-intensive Epyc X processor line after a three-year gap, according to The Register, with the new Venice-X chips scheduled to begin shipping in the second half of 2027. The processors leverage AMD's 3D V-Cache technology to triple L3 cache density beyond one gigabyte while supporting up to 96 cores, targeting latency-sensitive workloads in technical and scientific computing fields like computational fluid dynamics and electronic design automation. The chips were initially unveiled at CES earlier this year.
The Venice-X processors attach a 96 MB SRAM tile to each of up to eight CPU dies using advanced packaging, delivering 144 MB of L3 cache per chiplet and 1,152 MB per socket—matching the capacity of the Genoa-X parts they replace. Clock speeds have jumped significantly, with Venice-X reaching 5.3 GHz compared to Genoa-X's 3.7 GHz maximum. AMD achieved this by relocating the SRAM tile from atop the compute chiplets to beneath them, removing the thermal blanket effect that previously limited boost frequencies. The company's earlier Milan and Genoa X-series chips, which launched in 2022 and 2023 respectively, forced customers to choose between high frequency and expanded cache, but Venice-X eliminates that compromise. AMD skipped the Turin generation entirely for X-series parts, with the 5th-gen Epyc lineup unveiled in late 2024 containing no Turin-X variant.
According to Madhu Rangarajan, who oversees AMD's compute and enterprise AI products division, the company intentionally doesn't release X-series chips every generation because "the enterprise HPC kind of market tends to have a cadence that's a little bit slower." AMD Fellow Phil Steinke explained that keeping more of the computational model in cache reduces the time CPU cores spend waiting for data to transfer to and from system memory. Rangarajan believes the elimination of the frequency-versus-cache trade-off may broaden adoption, telling The Register he expects Venice-X "is going to end up being much bigger in HPC than the previous generations."
The decision to use stacked memory rather than simply disabling cores on higher-core-count chips came down to frequency requirements, the report notes. AMD's top-specification Venice CPUs already offer 256 cores with 1,024 MB of L3 cache, and the company could theoretically disable 160 cores to achieve a similar cache-per-core ratio—an approach it used for the Turin generation's Epyc 9175F, which fused off 112 cores from a 128-core design to create a 16-core part with 512 MB of cache. But such an approach would cap maximum frequency at 4.1 GHz rather than Venice-X's 5.3 GHz. AMD has relied on EDA workloads like functional verification testing for its own chip design, using simulation to verify silicon behaves as intended before manufacturing. Rangarajan framed Venice-X as a watershed moment, stating it marks "the first time you can get the larger L3 in our highest frequency part."
The Venice-X launch represents AMD's bet that the slower upgrade cycles in high-performance computing justify skipping processor generations for specialized variants, allowing the company to concentrate engineering resources where architectural improvements deliver the greatest performance gains. For enterprise buyers who've long balanced cache capacity against clock speed when selecting processors, the convergence of both attributes in a single SKU may reshape procurement strategies across technical computing environments.