Nvidia is evaluating three lower-memory configurations for its next flagship training chip, Rubin Ultra, after the company determined it may not secure enough high-bandwidth memory to meet original specifications, according to a report published by AI Weekly. The report, which corroborates earlier reporting from The Information, says the company has stopped treating Rubin Ultra's memory specification as final and is now weighing alternatives that reduce capacity per chip. The shift represents an unusual step backward for a flagship AI accelerator, where expanding memory per package has been the standard expectation across roadmaps for the past two years.
The three configurations under consideration replace the original 12-Hi HBM4e design with 8-Hi HBM4e, 12-Hi HBM4, and 8-Hi HBM4 options, the report says. The mainline Rubin Ultra variant now being shown to customers reportedly maintains peak theoretical FLOPS on HBM4 but cuts memory to 8-Hi and 192GB, which falls below Rubin's existing 12-Hi 288GB configuration. That represents roughly two-thirds of the capacity buyers had anticipated based on earlier guidance. The report traces the trajectory of Rubin Ultra spec reductions from the 4-die 1TB HBM4E 16-Hi configuration previewed at GTC 2025, through HBM4E 12-Hi, to a canceled 4-die multi-chip module, and finally to the current 2-die package. On power, an 1800W Max-Q is expected to become the mainstream option, with a 1200W variant aimed at lower-compute workloads such as token decoding and a 2600 to 2800W Max-P configuration at the high end.
TrendForce attributes the rollback to constrained DRAM supply extending through 2027, uncertain validation schedules for 12-Hi HBM4e, and data-center power shortages, according to the report. The analysis emphasizes these are described as options Nvidia is evaluating, with no final decision reached and the possibility that the eventual product mix could still shift. The report notes the analysis doesn't break down how much of the reduction stems from HBM supply constraints versus power limitations versus cost considerations, nor which hyperscaler customers have approved the lower specification.
The memory reduction carries immediate planning consequences for organizations building training clusters. Memory capacity per GPU determines how much of a model each node can hold, meaning buyers who structured infrastructure plans around 288GB per Rubin Ultra chip will need to revise architectures around approximately two-thirds of that figure. If the mainline product settles at 192GB, memory suppliers that achieve 12-Hi HBM4e validation first will still have an opportunity to supply the higher-tier configuration, while customers whose actual workloads center on token decoding rather than training the largest possible models may find the 1200W variant better suited to their needs than the flagship chip regardless of the memory question. The silicon itself isn't the problem, the report stresses—the constraints originate in the supply chain and infrastructure, not in the chip design. For enterprises already wrestling with power availability in existing data centers, the lower-wattage options may solve one bottleneck even as they create another in memory capacity. The final SKU mix will determine whether Nvidia's flagship generation becomes defined more by what it can't deliver than by what it can.