Scientists in South Korea have developed a method to dictate where ultrathin semiconductor crystals begin forming on wafers, achieving a 99.3 percent success rate in a test that could help bring the technology to mass production. The technique, detailed in a paper published October 7 in Nature by researchers from KAIST and startup TDS Innovation, addresses a longstanding barrier to manufacturing next-generation chips from atomically thin materials. Until now, these crystals have started growing at unpredictable locations, creating defects that hurt performance.
The team tested their approach on a two-centimeter substrate patterned with 400 designated growth sites. Single crystals formed at the intended center point in 397 of those locations, according to the study. The researchers also built working field-effect transistors using the process and reported higher charge-carrier mobility—a measurement of how easily electrical charge flows through the material—than previously recorded for selectively grown molybdenum disulfide transistors. The problem they're solving stems from how two-dimensional semiconductors typically grow: crystals start forming at random spots, and when multiple crystals expand and collide, the boundaries between them degrade electrical properties and create inconsistent devices.
The paper, titled "Spatially deterministic nucleation of 2D semiconductors by etching flux," describes what the authors call an etching-flux-mediated single-centred nucleation process. The technique uses oxygen released from an oxide barrier to create a lateral etching flux that prevents new crystals from forming anywhere in each patterned region except at its geometric center. Paper co-author Kibum Kang, who serves as co-CEO of TDS Innovation, stated that "building on this ability to control where crystal growth begins, we will form high-quality 2D single crystals uniformly where we want them and develop it into a next-generation semiconductor process that brings logic and memory closer together."
Why this matters: two-dimensional semiconductors are atomically thin layers—graphene is a single sheet of carbon atoms—being explored as building blocks for future transistors and other nanoscale components. Materials like molybdenum disulfide have an intrinsic band gap that makes them suitable for switching transistors, unlike graphene. Stacking these 2D devices on silicon chips could pack logic and memory into tighter spaces, cutting the distance and energy needed to shuttle data between them, according to TDS Innovation. The materials are also candidates for complementary field-effect transistors, or CFETs, which layer n-type and p-type transistors vertically rather than side by side—a 3D stacking approach that IBM and Intel have demonstrated. The 99.3 percent yield is encouraging for scaling up, though it doesn't yet represent commercial chip manufacturing.
TDS Innovation's Jony Jung said the company is targeting commercial use of two-dimensional semiconductors around 2030, and believes growing demand from AI—including physical AI and robotics—could accelerate adoption, though production timing hinges on additional validation. The breakthrough gives chipmakers a potential path to controlling crystal formation with the precision needed for mass production, which has been elusive with atomically thin materials. If the stacking approach works at scale, it could reshape how processors and memory are designed, pushing more capability into smaller footprints. The semiconductor industry faces mounting pressure to innovate beyond traditional scaling limits, and materials that can be layered atom by atom represent one avenue forward if manufacturing challenges like random crystal nucleation can be solved.